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      1-14-Vivado时序约束中Tcl命令的对象及属性
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    <p>发布于：2020年6月24日</p>
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      <h2 id="Vivado时序约束中Tcl命令的对象及属性"><a href="#Vivado时序约束中Tcl命令的对象及属性" class="headerlink" title="Vivado时序约束中Tcl命令的对象及属性"></a>Vivado时序约束中Tcl命令的对象及属性</h2><p>&emsp;&emsp;在前面的章节中，我们用了很多Tcl的指令，但有些指令并没有把所有的参数多列出来解释，这一节，我们就把约束中的Tcl指令详细讲一下。</p>
<p>我们前面讲到过<code>get_pins</code>和<code>get_ports</code>的区别，而且我们也用过<code>get_cells</code>、<code>get_clocks</code>和<code>get_nets</code>这几个指令，下面就通过一张图直观展现它们的区别。</p>
      
        
          
        
      
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      1-13-Vivado时序约束辅助工具
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    <p>发布于：2020年6月18日</p>
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      <h2 id="时序约束辅助工具"><a href="#时序约束辅助工具" class="headerlink" title="时序约束辅助工具"></a>时序约束辅助工具</h2><p>&emsp;&emsp;上面我们讲的都是xdc文件的方式进行时序约束，Vivado中还提供了两种图形界面的方式，帮我们进行时序约束：时序约束编辑器（Edit Timing Constraints ）和时序约束向导（Constraints Wizard）。两者都可以在综合或实现后的Design中打开。</p>
      
        
          
        
      
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      1-12-FPGA时序约束实战篇之多周期路径约束
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    <p>发布于：2020年6月16日</p>
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      <h3 id="多周期路径约束"><a href="#多周期路径约束" class="headerlink" title="多周期路径约束"></a>多周期路径约束</h3><p>&emsp;&emsp;多周期路径，我们一般按照以下4个步骤来约束：</p>
<ol>
<li>带有使能的数据</li>
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<p>&emsp;&emsp;首先来看带有使能的数据，在本工程中的Tming Report中，也提示了同一个时钟域之间的几个路径建立时间不满足要求</p>
      
        
          
        
      
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    <p>发布于：2020年6月15日</p>
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      <h3 id="5-伪路径约束"><a href="#5-伪路径约束" class="headerlink" title="5. 伪路径约束"></a>5. 伪路径约束</h3><p>&emsp;&emsp;在不加伪路径的时序约束时，Timing Report会提示很多的error，其中就有跨时钟域的error。</p>
      
        
          
        
      
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      1-10-FPGA时序约束实战篇之延迟约束
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    <p>发布于：2020年6月13日</p>
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      <h3 id="延迟约束"><a href="#延迟约束" class="headerlink" title="延迟约束"></a>延迟约束</h3><p>&emsp;&emsp;对于延迟约束，相信很多同学是不怎么用的，主要可能就是不熟悉这个约束，也有的是嫌麻烦，因为有时还要计算PCB上的走线延迟导致的时间差。而且不加延迟约束，Vivado也只是在Timing Report中提示warning，并不会导致时序错误，这也会让很多同学误以为这个约束可有可无。</p>
      
        
          
        
      
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    <p>发布于：2020年6月12日</p>
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      <h3 id="约束衍生时钟"><a href="#约束衍生时钟" class="headerlink" title="约束衍生时钟"></a>约束衍生时钟</h3><p>&emsp;&emsp;系统中有4个衍生时钟，但其中有两个是MMCM输出的，不需要我们手动约束，因此我们只需要对<code>clk_samp</code>和<code>spi_clk</code>进行约束即可。约束如下：</p>
<figure class="highlight plain"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br></pre></td><td class="code"><pre><span class="line">create_generated_clock -name clk_samp -source [get_pins clk_gen_i0&#x2F;clk_core_i0&#x2F;clk_tx] -divide_by 32 [get_pins clk_gen_i0&#x2F;BUFHCE_clk_samp_i0&#x2F;O]</span><br><span class="line">create_generated_clock -name spi_clk -source [get_pins dac_spi_i0&#x2F;out_ddr_flop_spi_clk_i0&#x2F;ODDR_inst&#x2F;C] -divide_by 1 -invert [get_ports spi_clk_pin]</span><br></pre></td></tr></table></figure>
      
        
          
        
      
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    <p>发布于：2020年6月10日</p>
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        console.info('Action:', e.action);
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   * @param message 提示信息
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   * @param time 消失时间
   */
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